1. Field of the Invention
The present invention relates to Dynamic Random Accessible Memory (DRAM). More particularly, this invention relates to DRAM fabricated by slightly modifying a conventional logic process. This invention further relates to the on-chip generation of precision voltages for the operation of DRAM embedded or fabricated using a conventional logic process.
2. Related Art
FIG. 1A is a schematic diagram of a conventional DRAM cell 100 that is fabricated using a conventional logic process. FIG. 1B is a cross sectional view of DRAM cell 100. As used herein, a conventional logic process is defined as a semiconductor fabrication process that uses only one layer of polysilicon and provides for either a single-well or twin-well structure. DRAM cell 100 consists of a p-channel MOS access transistor 1 having a gate terminal 9 connected to word line 3, a drain terminal 17 connected to bit line 5, and a source terminal 18 connected to the gate 11 of a p-channel MOS transistor 2. The connection between source terminal 18 and the gate 11 undesirably increases the layout area of DRAM cell 100. P-channel transistor 2 is configured to operate as a charge storage capacitor. The source and drain 19 of transistor 2 are commonly connected. The source, drain and channel of transistor 2 are connected to receive a fixed plate bias voltage Vpp. The Vpp voltage is a positive boosted voltage that is higher than the positive supply voltage Vdd by more than a transistor threshold voltage Vt.
As used herein, the electrode of the charge storage capacitor is defined as the node coupled to the access transistor, and the counter-electrode of the charge storage capacitor is defined as the node coupled to receive a fixed plate bias voltage. Thus, in DRAM cell 100, the gate 11 of transistor 2 forms the electrode of the charge storage capacitor, and the channel region of transistor 2 forms the counter-electrode of the charge storage capacitor.
To improve soft-error-rate sensitivity of DRAM cell 100, the cell is fabricated in an n-well region 14 which is located in a p-type substrate 8. To minimize the sub-threshold leakage of access transistor 1, n-well 14 is biased at the Vpp voltage (at n-type contact region 21). However, such a well bias increases the junction leakage. As a result, the bias voltage of n-well 14 is selected such that the sub-threshold leakage is reduced without significantly increasing the junction leakage. When storing charge in the storage capacitor, bit line 5 is brought to the appropriate level (i.e., Vdd or VSS) and word line 3 is activated to turn on access transistor 1. As a result, the electrode of the storage capacitor is charged. To maximize the stored charge, word line 3 is required to be driven to a negative boosted voltage Vbb that is lower than the supply voltage VSS minus the absolute value of the threshold voltage (Vtp) of access transistor 1.
In the data retention state, access transistor 1 is turned off by driving word line 3 to the Vdd supply voltage. To maximize the charge storage of the capacitor, the counter electrode is biased at the positive boosted voltage Vpp. The plate voltage Vpp is limited by the oxide breakdown voltage of the transistor 2 forming the charge storage capacitor.
DRAM cell 100 and its variations are documented in U.S. Pat. No. 5,600,598, entitled xe2x80x9cMemory Cell and Wordline Driver For Embedded DRAM in ASIC Process,xe2x80x9d by K. Skjaveland, R. Township, P. Gillingham (hereinafter referred to as xe2x80x9cSkjaveland et al.xe2x80x9d), and xe2x80x9cA 768k Embedded DRAM for 1.244 Gb.s ATM Switch in a 0.8 um Logic Process,xe2x80x9d P. Gillingham, B. Hold, I. Mes, C. O""Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow, Digest of ISSCC, 1996, pp. 262-263 (hereinafter referred to as xe2x80x9cGillingham et al.). Both Skjaveland et al. and Gillingham et al. describe memory cells that are contained in an n-well formed in a p-type substrate.
FIG. 2 is a schematic diagram of a word line control circuit 200 including a word line driver circuit 201 and a word line boost generator 202 described by Gillingham et al. Word line control circuit 200 includes p-channel transistors 211-217, inverters 221-229, NAND gates 231-232 and NOR gate 241, which are connected as illustrated. Word line driver 201 includes p-channel pull up transistor 211, which enables an associated word line to be pulled up to the Vdd supply voltage. P-channel pull down transistors 212-217 are provided so that the word line can be boosted down to a negative voltage (i.e., xe2x88x921.5V) substantially below the negative supply voltage VSS. However, the p-channel pull down transistors 212-217 have a drive capability much smaller (approximately half) than an NMOS transistor of similar size. As a result, the word line turn on of Gillingham et al. is relatively slow ( greater than 10 ns). Furthermore, in the data retention state, word line driver 201 only drives the word line to the Vdd supply voltage. As a result, the sub-threshold leakage of the access transistor in the memory cells may not be adequately suppressed.
DRAM cells similar to DRAM cell 100 have also been formed using n-channel transistors fabricated in a p-type well region. To maximize stored charge in such n-channel DRAM cells during memory cell access, the associated word line is driven to a voltage higher than the supply voltage Vdd plus the absolute value of the threshold voltage (Vtn) of the access transistor. In the data retention state, the n-channel access transistor is turned off by driving the word line to VSS supply voltage (0 Volts). To maximize the charge storage of the capacitor in an n-channel DRAM cell, the counter electrode is biased at a plate voltage Vbb that is lower than the VSS supply voltage.
A prior art scheme using n-channel DRAM cells includes the one described by Hashimoto et al. in xe2x80x9cAn Embedded DRAM Module using a Dual Sense Amplifier Architecture in a Logic Processxe2x80x9d, 1997 IEEE International Solid-State Circuits Conference, pp. 64-65 and 431. A p-type substrate is used, such that the memory cells are directly in contact with the substrate and are not isolated by any well structure. In the described design, substrate bias is not permitted. Moreover, application of a negative voltage to the word line is not applicable to ASICs that restrict substrate biasing to be zero. Consequently, the architecture achieves a negative gate-to-source voltage (Vgs) by limiting bit line swing. The negative Vgs voltage reduces sub-threshold leakage in the memory cells. Hashimoto et al. fails to describe the structure of the word line driver.
It would therefore be desirable to have a word line driver circuit that improves the leakage currents in DRAM cells fabricated using a conventional logic process. Moreover, it would be desirable to have improved methods for biasing DRAM cells fabricated using a conventional logic process.
Accordingly, the present invention provides a memory system that includes a dynamic random access memory (DRAM) cell, a word line, and a CMOS word line driver fabricated using a conventional logic process.
In another embodiment of the present invention, a DRAM cell is fabricated by slightly modifying a conventional logic process. In this embodiment, the DRAM cell is fabricated by forming the gate electrode of an access transistor from a first conductive layer, and then forming a capacitor structure. In one embodiment, the capacitor structure is fabricated by forming a crown electrode of a capacitor structure from a second conductive layer, forming a dielectric layer over the crown electrode, and then forming an plate electrode over the dielectric layer from a third conductive layer. A first set of thermal cycles are performed during the formation of the capacitor structure. After the capacitor structure has been formed, P+ and/or N+ ion implantations are performed, thereby forming shallow junctions on the chip (e.g., a drain region of the access transistor). Salicide is subsequently formed over the resulting structure. A second set of thermal cycles are performed to activate the implanted P+ and/or N+ impurities and the salicide. In the described embodiment, the second set of thermal cycles are comparable or less than the first set of thermal cycles. Because the first set of thermal cycles are performed prior to forming the N+ and P+ shallow junctions and salicide, the N+ and P+ shallow junctions and salicide are not adversely affected by the first set of thermal cycles.
In a particular embodiment, the crown electrode has a base region with vertical walls that extend upward from the base region. A dielectric layer, such as ONO, is located over the crown electrode. The plate electrode is located over the dielectric layer, such that the plate electrode extends over at least the interior surfaces of vertical walls of the crown electrode. The plate electrode can additionally extend over the exterior surfaces of the vertical walls of the crown electrode. The configuration of the crown electrode and plate electrode advantageously results in a DRAM cell having a small layout area.
The word line driver is controlled to selectively provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell.
A positive boosted voltage generator is provided to generate the positive boosted voltage, such that the positive boosted voltage is greater than the Vdd supply voltage but less than the Vdd supply voltage plus the absolute value of a transistor threshold voltage Vt.
Similarly, a negative boosted voltage generator is provided to generate the negative boosted voltage, such that the negative boosted voltage is less than the VSS supply voltage, but greater than the VSS supply voltage minus the absolute value of a transistor threshold voltage Vt.
A coupling circuit is provided between the word line driver and one of the positive or negative boosted voltage generators. For example, if the DRAM cell is constructed from PMOS transistors, then the coupling circuit couples the word line driver to the negative boosted word line generator. When the DRAM cell is being accessed, the coupling circuit couples the word line driver to the negative boosted voltage, thereby turning on the p-channel access transistor of the DRAM cell. However, when the DRAM cell is not being accessed, the coupling circuit couples the word line driver to the VSS supply voltage, thereby minimizing leakage currents associated with the negative boosted voltage.
In this embodiment, the coupling circuit can be configured to provide the VSS supply voltage to the word line driver when the word line is first activated. When the voltage on the word line falls below the Vdd supply voltage, the coupling circuit provides the negative boosted voltage to the word line driver.
Conversely, if the DRAM cell is constructed from NMOS transistors, then the coupling circuit couples the word line driver to the positive boosted word line generator. When the DRAM cell is being accessed, the coupling circuit couples the word line driver to the positive boosted voltage, thereby turning on the n-channel access transistor of the DRAM cell. However, when the DRAM cell is not being accessed, the coupling circuit couples the word line driver to the Vdd supply voltage, thereby minimizing leakage currents associated with the positive boosted voltage.
In this embodiment, the coupling circuit can be configured to provide the Vdd supply voltage to the word line driver when the word line is first activated. When the voltage on the word line rises above the VSS supply voltage, the coupling circuit provides the positive boosted voltage to the word line driver.
The positive boosted voltage generator includes a charge pump control circuit that limits the positive boosted voltage to a voltage less than Vdd plus Vt. Similarly, the negative boosted voltage generator includes a charge pump control circuit that limits the negative boosted voltage to a voltage greater than VSS minus Vt. The positive and negative boosted voltages are limited in this manner because, for normal logic applications using sub 0.25 micron processes, the gate oxide breakdown voltage is usually less than a threshold voltage Vt above the positive supply voltage Vdd.
The positive boosted voltage generator includes a charge pump control circuit that limits the positive boosted voltage to a voltage that is greater than the Vdd supply voltage by less than one transistor threshold voltage. In one embodiment, this charge pump control circuit includes a first p-channel transistor having a source coupled to the Vdd supply voltage and a drain coupled to a first reference current source. The gate of the first p-channel transistor is coupled to the gate of a second p-channel transistor. The first and second p-channel transistors have first and second channel widths, respectively, wherein the second channel width is greater than the first channel width. A second reference current source is coupled to the drain of the second p-channel transistor. The drain of the second p-channel transistor provides an inhibit control signal for the charge pump control circuit. A third p-channel transistor has a gate and a drain connected to a source of the second p-channel transistor, and a source coupled to receive the positive boosted voltage. The ratio of the first and second channel widths is selected such that the inhibit control signal is asserted when positive boosted voltage is less than one transistor threshold voltage greater than the Vdd supply voltage. In one embodiment, the first reference current source has a negative temperature coefficient to compensate for temperature effects of the second p-channel transistor. The second reference current source can be provided with a positive temperature coefficient to compensate for temperature effects of the third p-channel transistor.
Similarly, the negative boosted voltage generator includes a charge pump control circuit that limits the negative boosted voltage to a voltage that is less than the VSS supply voltage by less than one transistor threshold voltage Vt. In one embodiment, this charge pump control circuit includes a first n-channel transistor having a source coupled to the VSS supply voltage and a drain coupled to a first reference current source. The gate of the first n-channel transistor is coupled to the gate of a second n-channel transistor. The first and second n-channel transistors have first and second channel widths, respectively, wherein the second channel width is greater than the first channel width. A second reference current source is coupled to the drain of the second n-channel transistor. The drain of the second n-channel transistor provides an inhibit control signal for the charge pump control circuit. A p-channel transistor has a source coupled to the source of the second n-channel transistor, and a drain and gate coupled to receive the negative boosted voltage. The ratio of the first and second channel widths is selected such that the inhibit control signal is asserted when negative boosted voltage is greater than the VSS supply voltage minus the absolute value of a transistor threshold voltage Vt. In one embodiment, the first reference current source has a negative temperature coefficient to compensate for temperature effects of the second n-channel transistor. The second reference current source can be provided with a positive temperature coefficient to compensate for temperature effects of the p-channel transistor.
The present invention will be more fully understood in view of the following description and drawings.